Electronic Design

eGaN® FET-Silicon Power Shoot-Out Vol. 13, Part 2: Optimal PCB Layout

With the significant reduction in package parasitics provided by the eGaN FET, the package inductance is minimized and is no longer the major parasitic loss contributor. The high frequency loop ...
EDN

Modeling and Loop Compensation Design of Switching Mode Power Supplies, Part 2

In Figures 16 and 21, the power stage Gcv(s) with closed current loop is determined by the selection of power stage components, which are mainly decided by the DC ...
Electronic Design

eGaN® FET-Silicon Power Shoot-Out Vol. 13, Part 1: Impact Of Parasitics

Fig. 1. Ideal hard switching showing: (a) Turn-off transition and (b) Turn-on transition. During the voltage rising period, the device encounters both current and voltage in the device, resulting in ...
Semiconductor Engineering

PCB Layout Tips For Low Side Gate Drivers With OCP

Our 1ED44173/5/6 are the new low side gate driver ICs that integrate over-current protection (OCP), FAULT status output and enable function. This high integration level is excellent for the digitally ...
EDN

PCB design basics

This is the first of several articles in the PCB Design Best Practices series, which discusses the different steps of PCB development from the basics of creating a design schematic with specific ...